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Macros | Functions
icu.h File Reference

ICU helpers. More...

#include <teak/types.h>

Macros

#define REG_ICU_IRQ_ACK   (*(vu16 *)0x8202)
 ICU Interrupt Acknowledge (W)
 
#define REG_ICU_IRQ_DISABLE   (*(vu16 *)0x8252)
 ICU Interrupt Master Disable (R/W)
 
#define REG_ICU_IRQ_INT0   (*(vu16 *)0x8206)
 ICU Enable Interrupt routing to core interrupt 0 (R/W)
 
#define REG_ICU_IRQ_INT1   (*(vu16 *)0x8208)
 ICU Enable Interrupt routing to core interrupt 1 (R/W)
 
#define REG_ICU_IRQ_INT2   (*(vu16 *)0x820A)
 ICU Enable Interrupt routing to core interrupt 2 (R/W)
 
#define REG_ICU_IRQ_MODE   (*(vu16 *)0x820E)
 ICU Interrupt Trigger mode (0=Level, 1=Edge) (R/W)
 
#define REG_ICU_IRQ_PENDING   (*(vu16 *)0x8200)
 ICU Interrupt Pending Flags (R)
 
#define REG_ICU_IRQ_POLARITY   (*(vu16 *)0x8210)
 ICU Interrupt Polarity (0=Normal, 1=Invert) (R/W)
 
#define REG_ICU_IRQ_REQ   (*(vu16 *)0x8204)
 ICU Interrupt Manual Trigger (R/W)
 
#define REG_ICU_IRQ_VINT   (*(vu16 *)0x820C)
 ICU Enable Interrupt routing to vectored interrupt (R/W)
 
#define REG_ICU_VINT_ADDR_HI(x)   (*(vu16 *)(0x8212 + 4 * (x)))
 ICU Vectored Interrupt 0..15 Address, bit16-31 (R/W)
 
#define REG_ICU_VINT_ADDR_LO(x)   (*(vu16 *)(0x8214 + 4 * (x)))
 ICU Vectored Interrupt 0..15 Address, bit0-15 (R/W)
 

Functions

void icuInit (void)
 Initialize ICU unit and disable all interrupts.
 
void icuIrqDisable (u16 mask)
 Disable a peripheral IRQ.
 
void icuIrqSetup (u16 mask, int index)
 Route a peripheral IRQ to a CPU IRQ.
 

Detailed Description

ICU helpers.

The ICU helpers allow the developer to route peripheral interrupts (APBP, DMA, etc) to CPU interrupts 0 to 2.

Function Documentation

◆ icuIrqDisable()

void icuIrqDisable ( u16  mask)

Disable a peripheral IRQ.

Parameters
maskInterrupt mask. For example, ICU_IRQ_MASK_APBP.

◆ icuIrqSetup()

void icuIrqSetup ( u16  mask,
int  index 
)

Route a peripheral IRQ to a CPU IRQ.

The interrupt is setup as edge-triggered and normal polarity.

Parameters
maskInterrupt mask. For example, ICU_IRQ_MASK_APBP.
indexCPU interrupt to be triggered for the specified mask (0 to 2).